1. Field of the Invention
The present invention is related to memory devices, and more specifically to a dynamic word-line driver circuit having cascode-managed input and output stages.
2. Description of Related Art
Storage elements within memory devices such as dynamic random-access memories (DRAMS) are typically arranged in arrays of rows and columns. The storage elements, or storage cells, are accessed by activating word-lines that gate the storage cells of a particular row onto column bit-lines, which are evaluated to determine the contents of the storage cells.
While word-lines are used in both read and write operations, the word-lines for write operations, particularly in devices such as embedded DRAMS (eDRAMS) that are generally implemented using a single storage capacitor per cell, i.e., a single-transistor (1T) type storage cell, desirably has a higher voltage swing than a read bit-line or a write bit-line for an static random-access memory (SRAM) or a DRAM using 4T, 6T or even larger storage cells. However, the signals provided to the word-line driver are generally typical logic level and not high voltage. Therefore, level translators are typically provided in word-line drivers of devices such as eDRAMS. Level translators increase the amount of delay of the overall memory array, and therefore, there is a tradeoff in memory circuits between write speed, write confidence, and cell complexity. Further, special devices are generally required to handle the higher voltage produced by the word-line driver, leading to process requirements that could otherwise reduce the cost and simplify the manufacture of a memory circuit design.
Therefore, it would be desirable to provide a word-line driver circuit with improved delay characteristics and that does not require level translation stages or special higher-voltage devices to implement.